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High Speed Digital Design
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Holistic guide to signal integrity and interconnects with insider insights of Intel authors

Table of Contents

Transmission Line Fundamentals PCB Design for Signal Integrity Channel Modeling and Simulation Link Circuits and Architecture Measurement and Data Acquisition Techniques Designing and Validating with Intel Processors

About the Author

Hanqiao Zhang is an Analog Engineer at Intel and holds a PhD degree in Electromagnetics and Microwave Engineering from Clemson University. Hanqiao joined Intel Xeon product electrical validation team in 2011, where he worked on generations of Intel high-speed digital systems. He developed methodologies for validating high-speed interfaces, such as PCI Express and Quick Path Interface (QPI). Hanqiao is now a signal integrity engineer with Intel Data Center Group. He is involved in mission-critical high-performance servers signal integrity design, bring up, validation and debug. Steve Krooswyk has been at Intel since 2003 when we joined as a signal integrity engineer for EPSD server development. In 2009, Steve transitioned into the signal integrity lead for PCI Express in Intel's Enterprise Platform Technology Division (EPTD). In addition to server products, his experience includes involvement in the PCI Express 3.0 and 4.0 specifications. He holds a B.S. and M.S. in electrical engineering from the University of South Carolina. Jeffrey Ou joined Intel in 1999 as an analog design engineer in CMOS RF transceiver design. In 2006, Jeffrey transitioned to Xeon processor product design team in Server Development Group (SDG) developing a serial I/O module configurable for PCI Express and Quick Path Interface (QPI). Since then Jeffrey has been involved in several generations of Xeon products from design to post silicon validation. In 2012, Jeffrey was recognized as a tech lead in SDG, and continued to develop the cutting-edge high speed serial I/O modules for server products. Jeffrey holds a PhD degree in EECS from UC Berkeley and is a member of IEEE.

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